Developing new models for gem5

This is the index.

• Creating a `SimObject`
• Setting up your development environment
  • gem5-style guidelines
  • git branches
• Creating a very simple SimObject
  • Step 1: Create a Python class for your new SimObject
  • Step 2: Implement your SimObject in C++
  • Step 3: Register the SimObject and C++ file
  • Step 4: (Re)-build gem5
  • Step 5: Create the config scripts to use your new SimObject
• Debugging in gem5
  • Using debug flags
  • Adding a new debug flag
  • Debug output
  • Using functions other than DPRINTF
• Adding parameters to SimObjects and more events
  • Simple parameters
  • Other SimObjects as parameters
• Using events-driven programming in gem5
• Event-driven programming
• Creating a simple event callback
• Scheduling events
• More event scheduling
• Creating a SimObject in the memory system
• gem5 master and slave ports
  • Packets
  • Port interface
• Simple memory object example
  • Declare the SimObject
  • Define the SimpleMemobj class
  • Define a slave port type
  • Define a master port type
  • Defining the SimObject interface
  • Implementing basic SimObject functions
  • Implementing slave and master port functions
  • Implementing receiving requests
  • Implementing receiving responses
  • Create a config file
• Creating a full cache model
• SimpleCache SimObject
• Implementing the SimpleCache
  • Functional cache logic
• Creating a config file for the cache
• Adding statistics to the cache
• Instruction execution in gem5
• Translation in CPUs
• Overview of O3
• Steps to execute instruction (decode, execute/initiateAcc)
• Execution context
• Thread context
• Branch predictor
• Adding instructions to gem5
• Basics of an ISA
• ISA and CPU independence in gem5
• Concepts related to an ISA implementation in gem5
  • Static Instructions
  • Dynamic Instructions
  • Execution Context
  • Thread Context
• Journey of an instruction in gem5
• gem5 ISA parser
• Adding new instructions in gem5
• Testing newly added instructions in gem5
• Extending the memory system
• How classic caches work
• About Request, MemCmd, and Packets
• Developing cache coherence protocols in Ruby
• Ruby cache coherence model and SLICC language
• More on the relation between SLICC and C++ files in Ruby
• MSI example cache protocol
• First steps to writing a protocol
  • Writing a state machine file
• Ruby cache part 1: Creating a state machine in SLICC
• State machine parameters
• State declarations
• Event declarations
• User-defined structures
• Other declarations and definitions required
• Ruby Cache Part 23: In port code blocks
• Ruby cache part 3: Actions and transitions in state machines
• Action code blocks
• Transition code blocks
• Ruby Cache Part 4: MSI Directory implementation
• Ruby Cache Part 5: Building, configuring, and running the MSI cache
• Building the MSI protocol
  • The SLICC file
  • Compiling a protocol with SCons
• A configuration script for the MSI protocol
  • Cache system configuration
• Running the simple Ruby system
• Ruby Caches Part 6: Debugging Ruby protocols
• General debugging tips
• Understanding Protocol Traces
• Errors I ran into debugging MSI
• Ruby network and Garnet
• gem5's GPGPU model

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